feat: add clock configuration

This commit is contained in:
2025-07-23 22:41:28 +02:00
parent e36c8762d2
commit 9d5d6aff35

View File

@@ -33,10 +33,8 @@
interrupts = <TEGRA234_MAIN_GPIO(G, 3) IRQ_TYPE_LEVEL_HIGH>; interrupts = <TEGRA234_MAIN_GPIO(G, 3) IRQ_TYPE_LEVEL_HIGH>;
/* clock */ /* clock */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>; clocks = <&tc358743_refclk>;
clock-names = "refclk"; clock-names = "refclk";
assigned-clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>;
assigned-clock-rates = <27000000>;
refclk_hz = <27000000>; refclk_hz = <27000000>;
ports { ports {
@@ -125,5 +123,18 @@
}; };
}; };
}; };
};
/* clock configuration */
fragment@3 {
target-path = "/";
__overlay__ {
tc358743_refclk: tc358743-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "tc358743-refclk";
};
};
};
};